This invention relates to analog-digital converters, and more particularly to an analog-digital converter (which will be abbreviated hereinafter as an "ADC") which is suitable for handling a high-speed signal such as a video signal.
A prior art parallel ADC commonly known as a means suitable for handling a high-speed signal has generally a structure as shown in FIG. 1. Referring to FIG. 1, the prior art parallel ADC comprises (2.sup.n -1) comparators 11A (where n is the number of output bits) and an encoder (a code conversion circuit) 200. (The number of these comparators 11A is 2.sup.n when an overflow is taken into account.) A plurality of reference voltages V.sub.J obtained by voltage divider using resistor string and having different levels, for example, (2.sup.n -1) levels corresponding to a desired resolution are compared with an analog input voltage V.sub.IN by the (2.sup.n -1) comparators 11A respectively. The encoder 200 converts the output pattern of these comparators 11A into a corresponding binary-coded pattern. Each of the comparators 11A is composed of a comparing part 111A and an exclusive-OR circuit 121A. The comparing part 111A compares the input voltage V.sub.IN with the level of the reference voltage V.sub.J applied thereto.
Where the reference voltages V.sub.J are lower than the input voltage V.sub.IN, all of the corresponding comparing parts 111A generate outputs of high potential level (which will be expressed hereinafter as a "1"). On the other hand, where the reference voltages V.sub.J are higher than the input voltage V.sub.IN, all of the corresponding comparing parts 111A generate outputs of low potential level (which will be expressed hereinafter as a "0"). In the pair of the comparators 11A receiving the reference voltages V.sub.J of adjacent levels, the exclusive-OR circuits 121A detect coincidence between the outputs of the comparing parts 111A. Therefore, among the exclusive-OR circuits 121A in the comparators 11A, only one exclusive-OR circuit 121A corresponding to the position where the output of the associated comparing part 111A changes from a "0" to a "1", generates a "1" as its output, which each of all the remaining exclusive-OR circuits 121A generates a "0" as its output. That is, this exclusive-OR circuit 121A generating a "1" as its output corresponds to the level of the analog input voltage V.sub.IN. The outputs of all the comparators 11A are connected to individual corresponding bit wires of wired OR connections in the encoder 200.
In the parallel ADC having the structure described above, latching comparators are commonly employed to provide the comparing parts 111A of the comparators 11A. However, when a fast changing input signal is applied to the prior art parallel ADC, two or more of the exclusive-OR circuits 121A may generate a "1" as their outputs although normally only one exclusive-OR circuit 121A should generate a "1" as its output. Such a phenomenon is attributable to delayed arrival of the input signal at the individual comparators 11A and attributable also to delayed application of a clock signal to the individual latching comparators 111A.
In such a case, the digital output of the encoder (the code conversion circuit) 200 will be entirely different from the true digital equivalent of the analog input voltage V.sub.IN due to the wired-OR connections of the bit wires in the code conversion circuit 200, and false code error or missing code will result. In this case, serious false code error tends to occur especially at a change point between a high-order bit and a low-order bit. Suppose, for example, that one of the comparators 11A generates a "1" as its output to provide a digital output "011---11" in binary notation. However, when the next adjacent comparator 11A generates also a "1" as its output at the same time, the digital output of the code conversion circuit 200 is now given by "111---11" which is the logical sum (OR) of "011----11" and "100----00", and a serious error which is as large as 1/2 of the full scale will occur.
A method for avoiding occurrence of such an error in a prior art parallel ADC was proposed in a report entitled "A Monolithic 8-Bit A/D Converter with 120 MHz Conversion Rate Vol. SC-19 No. 6, December 1984". According to the method described in the report, a comparator group is divided into blocks at a change point between a high-order bit and a low-order bit, and the output of a code conversion circuit in a high-order block is used to gate the output of a code conversion circuit in a low-order block.
FIG. 2 shows the structure of part of such a parallel ADC based on the proposed method. Referring to FIG. 2, a plurality of voltage-dividing resistors R for providing a plurality of reference voltages having (2.sup.n -1) different levels are connected in series in each of blocks A, B and C, so that these blocks generate high-order bits and low-order bits as their outputs respectively. Suppose now that binary-coded outputs, for example, "0110" and "1001" are generated from the blocks A and B respectively. In such a case, the logical sum (OR) of "0110" and "1001" provides "1111", resulting in a very large error. In order to obviate such a defect, an inhibit circuit is provided in each of these blocks A and B in the ADC structure shown in FIG. 2, so that appearance of the encoder output from the low-order block A can be inhibited by the output (an inhibit signal S.sub.INH) of the inhibit circuit in the high-order block B. That is, the ADC shown in FIG. 2 is constructed so that the encoder outputs may not be simultaneously generated from the adjacent blocks A and B.
However, because the inhibit signal S.sub.INH produced on the basis of the outputs of some of the comparators in the high-order block is used to gate the encoder output of the low-order block in the prior art ADC shown in FIG. 2, a gate circuit must be provided for the bit wires in the encoder circuit in each of the blocks, and the size of each block gated by the inhibit signal S.sub.INH is determined by the number of the comparators connected to one encoder. That is, the size of each block is determined depending on the chip layout. Further, according to the method for gating the output of the low-order block by the inhibit signal S.sub.INH applied from the high-order block, undesirable false code error due to duplicate appearance of data in the same block cannot be prevented. Therefore, in order to prevent this false code error, the size of the block gated by the inhibit signal S.sub.INH is preferably suitably selected according to, for example, the number of bits handled by the ADC. However, this point has not been taken into account in the prior art ADC, and there has been such a problem that, when the blocks have a large size, a large error tends to occur due to duplicate appearance of data in the same block.